MWR-135B – measuring radio receiver

The receiver's local oscillator is built using a direct digital frequency synthesis (DDS) circuit and a modified PLL that downsizes the frequency using mixers instead of dividers. This provided a low level of phase noise (-139 dBc / Hz nominal at 10 kHz offset from the 1 GHz carrier), which allows receiving low-power signals near powerful interfering signals, as well as a high tuning rate. Spartan-6 level, has built-in 2 GB DDR memory. The processing power of the DSP board provides the following capabilities: A minimum RBW of 0.1 Hz, which expands the capabilities of working with low-power and ultra-narrowband signals 10 Gb / s I / O interface (Ethernet SFP +) for real-time transmission samples, complex or real spectra of signals with bandwidth up to 130 MHz per storage device or processing system. The duration of the recording is limited by the volume of the external storage device FPGA programming is available to the user Optionally, the RPU is supplied in a coherent synchronous two-channel implementation. In this configuration, the local oscillator, the ADC clock frequency generator, and the measurement start signal are common to both receive channels. Those. specifications Operating frequency range: 20 Hz – 4 GHz, 8.5 GHz, 10 GHz, 13.5 GHz (optional) Sensitivity at 25 ° C: -166 dBm / Hz (-164 dBm / Hz) Selectivity: 85 dB Dynamic range: 153 dB (148 dB) Number of antenna switch channels: 2